517 lines
17 KiB
Plaintext
517 lines
17 KiB
Plaintext
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/*
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* Distributed under the Boost Software License, Version 1.0.
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* (See accompanying file LICENSE_1_0.txt or copy at
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* http://www.boost.org/LICENSE_1_0.txt)
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*
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* Copyright (c) 2009 Helge Bahmann
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* Copyright (c) 2012 Tim Blechmann
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* Copyright (c) 2014 Andrey Semashev
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*/
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/*!
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* \file atomic/detail/ops_gcc_x86.hpp
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*
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* This header contains implementation of the \c operations template.
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*/
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#ifndef BOOST_ATOMIC_DETAIL_OPS_GCC_X86_HPP_INCLUDED_
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#define BOOST_ATOMIC_DETAIL_OPS_GCC_X86_HPP_INCLUDED_
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#include <boost/memory_order.hpp>
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#include <boost/atomic/detail/config.hpp>
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#include <boost/atomic/detail/storage_type.hpp>
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#include <boost/atomic/detail/operations_fwd.hpp>
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#include <boost/atomic/capabilities.hpp>
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#if defined(BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG8B) || defined(BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG16B)
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#include <boost/atomic/detail/ops_gcc_x86_dcas.hpp>
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#include <boost/atomic/detail/ops_cas_based.hpp>
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#endif
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#ifdef BOOST_HAS_PRAGMA_ONCE
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#pragma once
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#endif
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#if defined(__x86_64__)
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#define BOOST_ATOMIC_DETAIL_TEMP_CAS_REGISTER "rdx"
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#else
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#define BOOST_ATOMIC_DETAIL_TEMP_CAS_REGISTER "edx"
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#endif
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namespace boost {
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namespace atomics {
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namespace detail {
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struct gcc_x86_operations_base
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{
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static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
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static BOOST_FORCEINLINE void fence_before(memory_order order) BOOST_NOEXCEPT
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{
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if ((order & memory_order_release) != 0)
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__asm__ __volatile__ ("" ::: "memory");
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}
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static BOOST_FORCEINLINE void fence_after(memory_order order) BOOST_NOEXCEPT
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{
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if ((order & memory_order_acquire) != 0)
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__asm__ __volatile__ ("" ::: "memory");
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}
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};
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template< typename T, typename Derived >
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struct gcc_x86_operations :
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public gcc_x86_operations_base
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{
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typedef T storage_type;
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static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
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{
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if (order != memory_order_seq_cst)
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{
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fence_before(order);
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storage = v;
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fence_after(order);
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}
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else
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{
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Derived::exchange(storage, v, order);
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}
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}
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static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
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{
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storage_type v = storage;
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fence_after(order);
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return v;
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}
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static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
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{
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return Derived::fetch_add(storage, -v, order);
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}
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static BOOST_FORCEINLINE bool compare_exchange_weak(
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storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
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{
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return Derived::compare_exchange_strong(storage, expected, desired, success_order, failure_order);
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}
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static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
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{
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return !!Derived::exchange(storage, (storage_type)1, order);
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}
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static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
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{
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store(storage, (storage_type)0, order);
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}
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static BOOST_FORCEINLINE bool is_lock_free(storage_type const volatile&) BOOST_NOEXCEPT
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{
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return true;
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}
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};
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template< bool Signed >
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struct operations< 1u, Signed > :
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public gcc_x86_operations< typename make_storage_type< 1u, Signed >::type, operations< 1u, Signed > >
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{
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typedef gcc_x86_operations< typename make_storage_type< 1u, Signed >::type, operations< 1u, Signed > > base_type;
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typedef typename base_type::storage_type storage_type;
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typedef typename make_storage_type< 1u, Signed >::aligned aligned_storage_type;
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static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
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{
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__asm__ __volatile__
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(
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"lock; xaddb %0, %1"
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: "+q" (v), "+m" (storage)
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:
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
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);
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return v;
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}
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static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
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{
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__asm__ __volatile__
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(
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"xchgb %0, %1"
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: "+q" (v), "+m" (storage)
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:
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: "memory"
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);
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return v;
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}
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static BOOST_FORCEINLINE bool compare_exchange_strong(
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storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order, memory_order) BOOST_NOEXCEPT
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{
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storage_type previous = expected;
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bool success;
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__asm__ __volatile__
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(
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"lock; cmpxchgb %3, %1\n\t"
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"sete %2"
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: "+a" (previous), "+m" (storage), "=q" (success)
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: "q" (desired)
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
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);
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expected = previous;
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return success;
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}
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#define BOOST_ATOMIC_DETAIL_CAS_LOOP(op, argument, result)\
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__asm__ __volatile__\
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(\
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"xor %%" BOOST_ATOMIC_DETAIL_TEMP_CAS_REGISTER ", %%" BOOST_ATOMIC_DETAIL_TEMP_CAS_REGISTER "\n\t"\
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".align 16\n\t"\
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"1: movb %[arg], %%dl\n\t"\
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op " %%al, %%dl\n\t"\
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"lock; cmpxchgb %%dl, %[storage]\n\t"\
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"jne 1b"\
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: [res] "+a" (result), [storage] "+m" (storage)\
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: [arg] "q" (argument)\
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA BOOST_ATOMIC_DETAIL_TEMP_CAS_REGISTER, "memory"\
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)
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static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
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{
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storage_type res = storage;
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BOOST_ATOMIC_DETAIL_CAS_LOOP("andb", v, res);
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return res;
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}
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static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
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{
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storage_type res = storage;
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BOOST_ATOMIC_DETAIL_CAS_LOOP("orb", v, res);
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return res;
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}
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static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
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{
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storage_type res = storage;
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BOOST_ATOMIC_DETAIL_CAS_LOOP("xorb", v, res);
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return res;
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}
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#undef BOOST_ATOMIC_DETAIL_CAS_LOOP
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};
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template< bool Signed >
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struct operations< 2u, Signed > :
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public gcc_x86_operations< typename make_storage_type< 2u, Signed >::type, operations< 2u, Signed > >
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{
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typedef gcc_x86_operations< typename make_storage_type< 2u, Signed >::type, operations< 2u, Signed > > base_type;
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typedef typename base_type::storage_type storage_type;
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typedef typename make_storage_type< 2u, Signed >::aligned aligned_storage_type;
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static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
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{
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__asm__ __volatile__
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(
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"lock; xaddw %0, %1"
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: "+q" (v), "+m" (storage)
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:
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
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);
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return v;
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}
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static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
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{
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__asm__ __volatile__
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(
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"xchgw %0, %1"
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: "+q" (v), "+m" (storage)
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:
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: "memory"
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);
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return v;
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}
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static BOOST_FORCEINLINE bool compare_exchange_strong(
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storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order, memory_order) BOOST_NOEXCEPT
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{
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storage_type previous = expected;
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bool success;
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__asm__ __volatile__
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(
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"lock; cmpxchgw %3, %1\n\t"
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"sete %2"
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: "+a" (previous), "+m" (storage), "=q" (success)
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: "q" (desired)
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
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);
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expected = previous;
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return success;
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}
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#define BOOST_ATOMIC_DETAIL_CAS_LOOP(op, argument, result)\
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__asm__ __volatile__\
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(\
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"xor %%" BOOST_ATOMIC_DETAIL_TEMP_CAS_REGISTER ", %%" BOOST_ATOMIC_DETAIL_TEMP_CAS_REGISTER "\n\t"\
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".align 16\n\t"\
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"1: movw %[arg], %%dx\n\t"\
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op " %%ax, %%dx\n\t"\
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"lock; cmpxchgw %%dx, %[storage]\n\t"\
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"jne 1b"\
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: [res] "+a" (result), [storage] "+m" (storage)\
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: [arg] "q" (argument)\
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA BOOST_ATOMIC_DETAIL_TEMP_CAS_REGISTER, "memory"\
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)
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static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
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{
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storage_type res = storage;
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BOOST_ATOMIC_DETAIL_CAS_LOOP("andw", v, res);
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return res;
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}
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static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
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{
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storage_type res = storage;
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BOOST_ATOMIC_DETAIL_CAS_LOOP("orw", v, res);
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return res;
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}
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static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
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{
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storage_type res = storage;
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BOOST_ATOMIC_DETAIL_CAS_LOOP("xorw", v, res);
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return res;
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}
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#undef BOOST_ATOMIC_DETAIL_CAS_LOOP
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};
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template< bool Signed >
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struct operations< 4u, Signed > :
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public gcc_x86_operations< typename make_storage_type< 4u, Signed >::type, operations< 4u, Signed > >
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{
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typedef gcc_x86_operations< typename make_storage_type< 4u, Signed >::type, operations< 4u, Signed > > base_type;
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typedef typename base_type::storage_type storage_type;
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typedef typename make_storage_type< 4u, Signed >::aligned aligned_storage_type;
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static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
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{
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__asm__ __volatile__
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(
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"lock; xaddl %0, %1"
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: "+r" (v), "+m" (storage)
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:
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
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);
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return v;
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}
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static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
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{
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__asm__ __volatile__
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(
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"xchgl %0, %1"
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: "+r" (v), "+m" (storage)
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:
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: "memory"
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);
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return v;
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}
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static BOOST_FORCEINLINE bool compare_exchange_strong(
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storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order, memory_order) BOOST_NOEXCEPT
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{
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storage_type previous = expected;
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bool success;
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__asm__ __volatile__
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(
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"lock; cmpxchgl %3, %1\n\t"
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"sete %2"
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: "+a" (previous), "+m" (storage), "=q" (success)
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: "r" (desired)
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
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);
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expected = previous;
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return success;
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}
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#define BOOST_ATOMIC_DETAIL_CAS_LOOP(op, argument, result)\
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__asm__ __volatile__\
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(\
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"xor %%" BOOST_ATOMIC_DETAIL_TEMP_CAS_REGISTER ", %%" BOOST_ATOMIC_DETAIL_TEMP_CAS_REGISTER "\n\t"\
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".align 16\n\t"\
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"1: movl %[arg], %%edx\n\t"\
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op " %%eax, %%edx\n\t"\
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"lock; cmpxchgl %%edx, %[storage]\n\t"\
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"jne 1b"\
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: [res] "+a" (result), [storage] "+m" (storage)\
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: [arg] "r" (argument)\
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA BOOST_ATOMIC_DETAIL_TEMP_CAS_REGISTER, "memory"\
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)
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static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
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{
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storage_type res = storage;
|
||
|
|
BOOST_ATOMIC_DETAIL_CAS_LOOP("andl", v, res);
|
||
|
|
return res;
|
||
|
|
}
|
||
|
|
|
||
|
|
static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
|
||
|
|
{
|
||
|
|
storage_type res = storage;
|
||
|
|
BOOST_ATOMIC_DETAIL_CAS_LOOP("orl", v, res);
|
||
|
|
return res;
|
||
|
|
}
|
||
|
|
|
||
|
|
static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
|
||
|
|
{
|
||
|
|
storage_type res = storage;
|
||
|
|
BOOST_ATOMIC_DETAIL_CAS_LOOP("xorl", v, res);
|
||
|
|
return res;
|
||
|
|
}
|
||
|
|
|
||
|
|
#undef BOOST_ATOMIC_DETAIL_CAS_LOOP
|
||
|
|
};
|
||
|
|
|
||
|
|
#if defined(BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG8B)
|
||
|
|
|
||
|
|
template< bool Signed >
|
||
|
|
struct operations< 8u, Signed > :
|
||
|
|
public cas_based_operations< gcc_dcas_x86< Signed > >
|
||
|
|
{
|
||
|
|
};
|
||
|
|
|
||
|
|
#elif defined(__x86_64__)
|
||
|
|
|
||
|
|
template< bool Signed >
|
||
|
|
struct operations< 8u, Signed > :
|
||
|
|
public gcc_x86_operations< typename make_storage_type< 8u, Signed >::type, operations< 8u, Signed > >
|
||
|
|
{
|
||
|
|
typedef gcc_x86_operations< typename make_storage_type< 8u, Signed >::type, operations< 8u, Signed > > base_type;
|
||
|
|
typedef typename base_type::storage_type storage_type;
|
||
|
|
typedef typename make_storage_type< 8u, Signed >::aligned aligned_storage_type;
|
||
|
|
|
||
|
|
static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
|
||
|
|
{
|
||
|
|
__asm__ __volatile__
|
||
|
|
(
|
||
|
|
"lock; xaddq %0, %1"
|
||
|
|
: "+r" (v), "+m" (storage)
|
||
|
|
:
|
||
|
|
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
|
||
|
|
);
|
||
|
|
return v;
|
||
|
|
}
|
||
|
|
|
||
|
|
static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
|
||
|
|
{
|
||
|
|
__asm__ __volatile__
|
||
|
|
(
|
||
|
|
"xchgq %0, %1"
|
||
|
|
: "+r" (v), "+m" (storage)
|
||
|
|
:
|
||
|
|
: "memory"
|
||
|
|
);
|
||
|
|
return v;
|
||
|
|
}
|
||
|
|
|
||
|
|
static BOOST_FORCEINLINE bool compare_exchange_strong(
|
||
|
|
storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order, memory_order) BOOST_NOEXCEPT
|
||
|
|
{
|
||
|
|
storage_type previous = expected;
|
||
|
|
bool success;
|
||
|
|
__asm__ __volatile__
|
||
|
|
(
|
||
|
|
"lock; cmpxchgq %3, %1\n\t"
|
||
|
|
"sete %2"
|
||
|
|
: "+a" (previous), "+m" (storage), "=q" (success)
|
||
|
|
: "r" (desired)
|
||
|
|
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
|
||
|
|
);
|
||
|
|
expected = previous;
|
||
|
|
return success;
|
||
|
|
}
|
||
|
|
|
||
|
|
#define BOOST_ATOMIC_DETAIL_CAS_LOOP(op, argument, result)\
|
||
|
|
__asm__ __volatile__\
|
||
|
|
(\
|
||
|
|
"xor %%" BOOST_ATOMIC_DETAIL_TEMP_CAS_REGISTER ", %%" BOOST_ATOMIC_DETAIL_TEMP_CAS_REGISTER "\n\t"\
|
||
|
|
".align 16\n\t"\
|
||
|
|
"1: movq %[arg], %%rdx\n\t"\
|
||
|
|
op " %%rax, %%rdx\n\t"\
|
||
|
|
"lock; cmpxchgq %%rdx, %[storage]\n\t"\
|
||
|
|
"jne 1b"\
|
||
|
|
: [res] "+a" (result), [storage] "+m" (storage)\
|
||
|
|
: [arg] "r" (argument)\
|
||
|
|
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA BOOST_ATOMIC_DETAIL_TEMP_CAS_REGISTER, "memory"\
|
||
|
|
)
|
||
|
|
|
||
|
|
static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
|
||
|
|
{
|
||
|
|
storage_type res = storage;
|
||
|
|
BOOST_ATOMIC_DETAIL_CAS_LOOP("andq", v, res);
|
||
|
|
return res;
|
||
|
|
}
|
||
|
|
|
||
|
|
static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
|
||
|
|
{
|
||
|
|
storage_type res = storage;
|
||
|
|
BOOST_ATOMIC_DETAIL_CAS_LOOP("orq", v, res);
|
||
|
|
return res;
|
||
|
|
}
|
||
|
|
|
||
|
|
static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
|
||
|
|
{
|
||
|
|
storage_type res = storage;
|
||
|
|
BOOST_ATOMIC_DETAIL_CAS_LOOP("xorq", v, res);
|
||
|
|
return res;
|
||
|
|
}
|
||
|
|
|
||
|
|
#undef BOOST_ATOMIC_DETAIL_CAS_LOOP
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG16B)
|
||
|
|
|
||
|
|
template< bool Signed >
|
||
|
|
struct operations< 16u, Signed > :
|
||
|
|
public cas_based_operations< gcc_dcas_x86_64< Signed > >
|
||
|
|
{
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif // defined(BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG16B)
|
||
|
|
|
||
|
|
BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
|
||
|
|
{
|
||
|
|
if (order == memory_order_seq_cst)
|
||
|
|
{
|
||
|
|
__asm__ __volatile__
|
||
|
|
(
|
||
|
|
#if defined(BOOST_ATOMIC_DETAIL_X86_HAS_MFENCE)
|
||
|
|
"mfence\n"
|
||
|
|
#else
|
||
|
|
"lock; addl $0, (%%esp)\n"
|
||
|
|
#endif
|
||
|
|
::: "memory"
|
||
|
|
);
|
||
|
|
}
|
||
|
|
else if ((order & (memory_order_acquire | memory_order_release)) != 0)
|
||
|
|
{
|
||
|
|
__asm__ __volatile__ ("" ::: "memory");
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
|
||
|
|
{
|
||
|
|
if (order != memory_order_relaxed)
|
||
|
|
__asm__ __volatile__ ("" ::: "memory");
|
||
|
|
}
|
||
|
|
|
||
|
|
} // namespace detail
|
||
|
|
} // namespace atomics
|
||
|
|
} // namespace boost
|
||
|
|
|
||
|
|
#undef BOOST_ATOMIC_DETAIL_TEMP_CAS_REGISTER
|
||
|
|
|
||
|
|
#endif // BOOST_ATOMIC_DETAIL_OPS_GCC_X86_HPP_INCLUDED_
|