Initial Commit
This commit is contained in:
Jordan Sherer
@@ -0,0 +1,975 @@
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/*
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* Distributed under the Boost Software License, Version 1.0.
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* (See accompanying file LICENSE_1_0.txt or copy at
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* http://www.boost.org/LICENSE_1_0.txt)
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*
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* Copyright (c) 2009 Helge Bahmann
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* Copyright (c) 2013 Tim Blechmann
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* Copyright (c) 2014 Andrey Semashev
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*/
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/*!
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* \file atomic/detail/ops_gcc_arm.hpp
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*
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* This header contains implementation of the \c operations template.
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*/
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#ifndef BOOST_ATOMIC_DETAIL_OPS_GCC_ARM_HPP_INCLUDED_
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#define BOOST_ATOMIC_DETAIL_OPS_GCC_ARM_HPP_INCLUDED_
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#include <boost/cstdint.hpp>
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#include <boost/memory_order.hpp>
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#include <boost/atomic/detail/config.hpp>
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#include <boost/atomic/detail/storage_type.hpp>
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#include <boost/atomic/detail/operations_fwd.hpp>
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#include <boost/atomic/detail/ops_extending_cas_based.hpp>
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#include <boost/atomic/capabilities.hpp>
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#ifdef BOOST_HAS_PRAGMA_ONCE
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#pragma once
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#endif
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namespace boost {
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namespace atomics {
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namespace detail {
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// From the ARM Architecture Reference Manual for architecture v6:
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//
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// LDREX{<cond>} <Rd>, [<Rn>]
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// <Rd> Specifies the destination register for the memory word addressed by <Rd>
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// <Rn> Specifies the register containing the address.
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//
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// STREX{<cond>} <Rd>, <Rm>, [<Rn>]
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// <Rd> Specifies the destination register for the returned status value.
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// 0 if the operation updates memory
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// 1 if the operation fails to update memory
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// <Rm> Specifies the register containing the word to be stored to memory.
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// <Rn> Specifies the register containing the address.
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// Rd must not be the same register as Rm or Rn.
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//
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// ARM v7 is like ARM v6 plus:
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// There are half-word and byte versions of the LDREX and STREX instructions,
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// LDREXH, LDREXB, STREXH and STREXB.
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// There are also double-word versions, LDREXD and STREXD.
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// (Actually it looks like these are available from version 6k onwards.)
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// FIXME these are not yet used; should be mostly a matter of copy-and-paste.
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// I think you can supply an immediate offset to the address.
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//
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// A memory barrier is effected using a "co-processor 15" instruction,
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// though a separate assembler mnemonic is available for it in v7.
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//
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// "Thumb 1" is a subset of the ARM instruction set that uses a 16-bit encoding. It
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// doesn't include all instructions and in particular it doesn't include the co-processor
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// instruction used for the memory barrier or the load-locked/store-conditional
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// instructions. So, if we're compiling in "Thumb 1" mode, we need to wrap all of our
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// asm blocks with code to temporarily change to ARM mode.
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//
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// You can only change between ARM and Thumb modes when branching using the bx instruction.
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// bx takes an address specified in a register. The least significant bit of the address
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// indicates the mode, so 1 is added to indicate that the destination code is Thumb.
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// A temporary register is needed for the address and is passed as an argument to these
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// macros. It must be one of the "low" registers accessible to Thumb code, specified
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// using the "l" attribute in the asm statement.
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//
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// Architecture v7 introduces "Thumb 2", which does include (almost?) all of the ARM
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// instruction set. (Actually, there was an extension of v6 called v6T2 which supported
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// "Thumb 2" mode, but its architecture manual is no longer available, referring to v7.)
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// So in v7 we don't need to change to ARM mode; we can write "universal
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// assembler" which will assemble to Thumb 2 or ARM code as appropriate. The only thing
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// we need to do to make this "universal" assembler mode work is to insert "IT" instructions
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// to annotate the conditional instructions. These are ignored in other modes (e.g. v6),
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// so they can always be present.
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// A note about memory_order_consume. Technically, this architecture allows to avoid
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// unnecessary memory barrier after consume load since it supports data dependency ordering.
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// However, some compiler optimizations may break a seemingly valid code relying on data
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// dependency tracking by injecting bogus branches to aid out of order execution.
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// This may happen not only in Boost.Atomic code but also in user's code, which we have no
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// control of. See this thread: http://lists.boost.org/Archives/boost/2014/06/213890.php.
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// For this reason we promote memory_order_consume to memory_order_acquire.
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#if defined(__thumb__) && !defined(__thumb2__)
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#define BOOST_ATOMIC_DETAIL_ARM_ASM_START(TMPREG) "adr " #TMPREG ", 8f\n" "bx " #TMPREG "\n" ".arm\n" ".align 4\n" "8:\n"
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#define BOOST_ATOMIC_DETAIL_ARM_ASM_END(TMPREG) "adr " #TMPREG ", 9f + 1\n" "bx " #TMPREG "\n" ".thumb\n" ".align 2\n" "9:\n"
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#define BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(var) "=&l" (var)
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#else
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// The tmpreg may be wasted in this case, which is non-optimal.
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#define BOOST_ATOMIC_DETAIL_ARM_ASM_START(TMPREG)
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#define BOOST_ATOMIC_DETAIL_ARM_ASM_END(TMPREG)
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#define BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(var) "=&r" (var)
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#endif
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struct gcc_arm_operations_base
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{
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static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
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static BOOST_FORCEINLINE void fence_before(memory_order order) BOOST_NOEXCEPT
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{
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if ((order & memory_order_release) != 0)
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hardware_full_fence();
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}
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static BOOST_FORCEINLINE void fence_after(memory_order order) BOOST_NOEXCEPT
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{
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if ((order & (memory_order_consume | memory_order_acquire)) != 0)
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hardware_full_fence();
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}
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static BOOST_FORCEINLINE void fence_after_store(memory_order order) BOOST_NOEXCEPT
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{
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if (order == memory_order_seq_cst)
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hardware_full_fence();
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}
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static BOOST_FORCEINLINE void hardware_full_fence() BOOST_NOEXCEPT
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{
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#if defined(BOOST_ATOMIC_DETAIL_ARM_HAS_DMB)
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// Older binutils (supposedly, older than 2.21.1) didn't support symbolic or numeric arguments of the "dmb" instruction such as "ish" or "#11".
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// As a workaround we have to inject encoded bytes of the instruction. There are two encodings for the instruction: ARM and Thumb. See ARM Architecture Reference Manual, A8.8.43.
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// Since we cannot detect binutils version at compile time, we'll have to always use this hack.
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__asm__ __volatile__
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(
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#if defined(__thumb2__)
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".short 0xF3BF, 0x8F5B\n" // dmb ish
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#else
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".word 0xF57FF05B\n" // dmb ish
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#endif
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:
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:
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: "memory"
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);
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#else
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int tmp;
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__asm__ __volatile__
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(
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BOOST_ATOMIC_DETAIL_ARM_ASM_START(%0)
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"mcr\tp15, 0, r0, c7, c10, 5\n"
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BOOST_ATOMIC_DETAIL_ARM_ASM_END(%0)
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: "=&l" (tmp)
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:
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: "memory"
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);
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#endif
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}
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};
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template< bool Signed >
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struct operations< 4u, Signed > :
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public gcc_arm_operations_base
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{
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typedef typename make_storage_type< 4u, Signed >::type storage_type;
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typedef typename make_storage_type< 4u, Signed >::aligned aligned_storage_type;
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static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
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{
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fence_before(order);
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storage = v;
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fence_after_store(order);
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}
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static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
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{
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storage_type v = storage;
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fence_after(order);
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return v;
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}
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static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
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{
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storage_type original;
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fence_before(order);
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uint32_t tmp;
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__asm__ __volatile__
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(
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BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
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"1:\n"
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"ldrex %[original], %[storage]\n" // load the original value
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"strex %[tmp], %[value], %[storage]\n" // store the replacement, tmp = store failed
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"teq %[tmp], #0\n" // check if store succeeded
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"bne 1b\n"
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BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
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: [tmp] "=&l" (tmp), [original] "=&r" (original), [storage] "+Q" (storage)
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: [value] "r" (v)
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
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);
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fence_after(order);
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return original;
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}
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static BOOST_FORCEINLINE bool compare_exchange_weak(
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storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
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{
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fence_before(success_order);
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uint32_t success;
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uint32_t tmp;
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storage_type original;
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__asm__ __volatile__
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(
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BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
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"mov %[success], #0\n" // success = 0
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"ldrex %[original], %[storage]\n" // original = *(&storage)
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"cmp %[original], %[expected]\n" // flags = original==expected
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"itt eq\n" // [hint that the following 2 instructions are conditional on flags.equal]
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"strexeq %[success], %[desired], %[storage]\n" // if (flags.equal) *(&storage) = desired, success = store failed
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"eoreq %[success], %[success], #1\n" // if (flags.equal) success ^= 1 (i.e. make it 1 if store succeeded)
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BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
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: [original] "=&r" (original), // %0
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[success] "=&r" (success), // %1
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[tmp] "=&l" (tmp), // %2
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[storage] "+Q" (storage) // %3
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: [expected] "r" (expected), // %4
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[desired] "r" (desired) // %5
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
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);
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if (success)
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fence_after(success_order);
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else
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fence_after(failure_order);
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expected = original;
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return !!success;
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}
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static BOOST_FORCEINLINE bool compare_exchange_strong(
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storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
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{
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fence_before(success_order);
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uint32_t success;
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uint32_t tmp;
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storage_type original;
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__asm__ __volatile__
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(
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BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
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"mov %[success], #0\n" // success = 0
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"1:\n"
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"ldrex %[original], %[storage]\n" // original = *(&storage)
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"cmp %[original], %[expected]\n" // flags = original==expected
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"bne 2f\n" // if (!flags.equal) goto end
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"strex %[success], %[desired], %[storage]\n" // *(&storage) = desired, success = store failed
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"eors %[success], %[success], #1\n" // success ^= 1 (i.e. make it 1 if store succeeded); flags.equal = success == 0
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"beq 1b\n" // if (flags.equal) goto retry
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"2:\n"
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BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
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: [original] "=&r" (original), // %0
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[success] "=&r" (success), // %1
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[tmp] "=&l" (tmp), // %2
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[storage] "+Q" (storage) // %3
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: [expected] "r" (expected), // %4
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[desired] "r" (desired) // %5
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
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);
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if (success)
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fence_after(success_order);
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else
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fence_after(failure_order);
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expected = original;
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return !!success;
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}
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static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
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{
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fence_before(order);
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uint32_t tmp;
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storage_type original, result;
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__asm__ __volatile__
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(
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BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
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"1:\n"
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"ldrex %[original], %[storage]\n" // original = *(&storage)
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"add %[result], %[original], %[value]\n" // result = original + value
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"strex %[tmp], %[result], %[storage]\n" // *(&storage) = result, tmp = store failed
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"teq %[tmp], #0\n" // flags = tmp==0
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"bne 1b\n" // if (!flags.equal) goto retry
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BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
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: [original] "=&r" (original), // %0
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[result] "=&r" (result), // %1
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[tmp] "=&l" (tmp), // %2
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[storage] "+Q" (storage) // %3
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: [value] "r" (v) // %4
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
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);
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fence_after(order);
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return original;
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}
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static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
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{
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fence_before(order);
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uint32_t tmp;
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storage_type original, result;
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__asm__ __volatile__
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(
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BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
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"1:\n"
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"ldrex %[original], %[storage]\n" // original = *(&storage)
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"sub %[result], %[original], %[value]\n" // result = original - value
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"strex %[tmp], %[result], %[storage]\n" // *(&storage) = result, tmp = store failed
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"teq %[tmp], #0\n" // flags = tmp==0
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"bne 1b\n" // if (!flags.equal) goto retry
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BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
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: [original] "=&r" (original), // %0
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[result] "=&r" (result), // %1
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[tmp] "=&l" (tmp), // %2
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[storage] "+Q" (storage) // %3
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: [value] "r" (v) // %4
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
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);
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fence_after(order);
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return original;
|
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}
|
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static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
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{
|
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fence_before(order);
|
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uint32_t tmp;
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storage_type original, result;
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__asm__ __volatile__
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(
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BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
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"1:\n"
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"ldrex %[original], %[storage]\n" // original = *(&storage)
|
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"and %[result], %[original], %[value]\n" // result = original & value
|
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"strex %[tmp], %[result], %[storage]\n" // *(&storage) = result, tmp = store failed
|
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"teq %[tmp], #0\n" // flags = tmp==0
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"bne 1b\n" // if (!flags.equal) goto retry
|
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BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
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: [original] "=&r" (original), // %0
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[result] "=&r" (result), // %1
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[tmp] "=&l" (tmp), // %2
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[storage] "+Q" (storage) // %3
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: [value] "r" (v) // %4
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
||||
);
|
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fence_after(order);
|
||||
return original;
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
fence_before(order);
|
||||
uint32_t tmp;
|
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storage_type original, result;
|
||||
__asm__ __volatile__
|
||||
(
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BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
|
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"1:\n"
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"ldrex %[original], %[storage]\n" // original = *(&storage)
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"orr %[result], %[original], %[value]\n" // result = original | value
|
||||
"strex %[tmp], %[result], %[storage]\n" // *(&storage) = result, tmp = store failed
|
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"teq %[tmp], #0\n" // flags = tmp==0
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"bne 1b\n" // if (!flags.equal) goto retry
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
|
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: [original] "=&r" (original), // %0
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||||
[result] "=&r" (result), // %1
|
||||
[tmp] "=&l" (tmp), // %2
|
||||
[storage] "+Q" (storage) // %3
|
||||
: [value] "r" (v) // %4
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
||||
);
|
||||
fence_after(order);
|
||||
return original;
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
fence_before(order);
|
||||
uint32_t tmp;
|
||||
storage_type original, result;
|
||||
__asm__ __volatile__
|
||||
(
|
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BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
|
||||
"1:\n"
|
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"ldrex %[original], %[storage]\n" // original = *(&storage)
|
||||
"eor %[result], %[original], %[value]\n" // result = original ^ value
|
||||
"strex %[tmp], %[result], %[storage]\n" // *(&storage) = result, tmp = store failed
|
||||
"teq %[tmp], #0\n" // flags = tmp==0
|
||||
"bne 1b\n" // if (!flags.equal) goto retry
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
|
||||
: [original] "=&r" (original), // %0
|
||||
[result] "=&r" (result), // %1
|
||||
[tmp] "=&l" (tmp), // %2
|
||||
[storage] "+Q" (storage) // %3
|
||||
: [value] "r" (v) // %4
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
||||
);
|
||||
fence_after(order);
|
||||
return original;
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
return !!exchange(storage, (storage_type)1, order);
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
store(storage, 0, order);
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE bool is_lock_free(storage_type const volatile&) BOOST_NOEXCEPT
|
||||
{
|
||||
return true;
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
template< >
|
||||
struct operations< 1u, false > :
|
||||
public operations< 4u, false >
|
||||
{
|
||||
typedef operations< 4u, false > base_type;
|
||||
typedef base_type::storage_type storage_type;
|
||||
|
||||
static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
fence_before(order);
|
||||
uint32_t tmp;
|
||||
storage_type original, result;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
|
||||
"1:\n"
|
||||
"ldrex %[original], %[storage]\n" // original = *(&storage)
|
||||
"add %[result], %[original], %[value]\n" // result = original + value
|
||||
"uxtb %[result], %[result]\n" // zero extend result from 8 to 32 bits
|
||||
"strex %[tmp], %[result], %[storage]\n" // *(&storage) = result, tmp = store failed
|
||||
"teq %[tmp], #0\n" // flags = tmp==0
|
||||
"bne 1b\n" // if (!flags.equal) goto retry
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
|
||||
: [original] "=&r" (original), // %0
|
||||
[result] "=&r" (result), // %1
|
||||
[tmp] "=&l" (tmp), // %2
|
||||
[storage] "+Q" (storage) // %3
|
||||
: [value] "r" (v) // %4
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
||||
);
|
||||
fence_after(order);
|
||||
return original;
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
fence_before(order);
|
||||
uint32_t tmp;
|
||||
storage_type original, result;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
|
||||
"1:\n"
|
||||
"ldrex %[original], %[storage]\n" // original = *(&storage)
|
||||
"sub %[result], %[original], %[value]\n" // result = original - value
|
||||
"uxtb %[result], %[result]\n" // zero extend result from 8 to 32 bits
|
||||
"strex %[tmp], %[result], %[storage]\n" // *(&storage) = result, tmp = store failed
|
||||
"teq %[tmp], #0\n" // flags = tmp==0
|
||||
"bne 1b\n" // if (!flags.equal) goto retry
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
|
||||
: [original] "=&r" (original), // %0
|
||||
[result] "=&r" (result), // %1
|
||||
[tmp] "=&l" (tmp), // %2
|
||||
[storage] "+Q" (storage) // %3
|
||||
: [value] "r" (v) // %4
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
||||
);
|
||||
fence_after(order);
|
||||
return original;
|
||||
}
|
||||
};
|
||||
|
||||
template< >
|
||||
struct operations< 1u, true > :
|
||||
public operations< 4u, true >
|
||||
{
|
||||
typedef operations< 4u, true > base_type;
|
||||
typedef base_type::storage_type storage_type;
|
||||
|
||||
static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
fence_before(order);
|
||||
uint32_t tmp;
|
||||
storage_type original, result;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
|
||||
"1:\n"
|
||||
"ldrex %[original], %[storage]\n" // original = *(&storage)
|
||||
"add %[result], %[original], %[value]\n" // result = original + value
|
||||
"sxtb %[result], %[result]\n" // sign extend result from 8 to 32 bits
|
||||
"strex %[tmp], %[result], %[storage]\n" // *(&storage) = result, tmp = store failed
|
||||
"teq %[tmp], #0\n" // flags = tmp==0
|
||||
"bne 1b\n" // if (!flags.equal) goto retry
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
|
||||
: [original] "=&r" (original), // %0
|
||||
[result] "=&r" (result), // %1
|
||||
[tmp] "=&l" (tmp), // %2
|
||||
[storage] "+Q" (storage) // %3
|
||||
: [value] "r" (v) // %4
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
||||
);
|
||||
fence_after(order);
|
||||
return original;
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
fence_before(order);
|
||||
uint32_t tmp;
|
||||
storage_type original, result;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
|
||||
"1:\n"
|
||||
"ldrex %[original], %[storage]\n" // original = *(&storage)
|
||||
"sub %[result], %[original], %[value]\n" // result = original - value
|
||||
"sxtb %[result], %[result]\n" // sign extend result from 8 to 32 bits
|
||||
"strex %[tmp], %[result], %[storage]\n" // *(&storage) = result, tmp = store failed
|
||||
"teq %[tmp], #0\n" // flags = tmp==0
|
||||
"bne 1b\n" // if (!flags.equal) goto retry
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
|
||||
: [original] "=&r" (original), // %0
|
||||
[result] "=&r" (result), // %1
|
||||
[tmp] "=&l" (tmp), // %2
|
||||
[storage] "+Q" (storage) // %3
|
||||
: [value] "r" (v) // %4
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
||||
);
|
||||
fence_after(order);
|
||||
return original;
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
template< >
|
||||
struct operations< 2u, false > :
|
||||
public operations< 4u, false >
|
||||
{
|
||||
typedef operations< 4u, false > base_type;
|
||||
typedef base_type::storage_type storage_type;
|
||||
|
||||
static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
fence_before(order);
|
||||
uint32_t tmp;
|
||||
storage_type original, result;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
|
||||
"1:\n"
|
||||
"ldrex %[original], %[storage]\n" // original = *(&storage)
|
||||
"add %[result], %[original], %[value]\n" // result = original + value
|
||||
"uxth %[result], %[result]\n" // zero extend result from 16 to 32 bits
|
||||
"strex %[tmp], %[result], %[storage]\n" // *(&storage) = result, tmp = store failed
|
||||
"teq %[tmp], #0\n" // flags = tmp==0
|
||||
"bne 1b\n" // if (!flags.equal) goto retry
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
|
||||
: [original] "=&r" (original), // %0
|
||||
[result] "=&r" (result), // %1
|
||||
[tmp] "=&l" (tmp), // %2
|
||||
[storage] "+Q" (storage) // %3
|
||||
: [value] "r" (v) // %4
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
||||
);
|
||||
fence_after(order);
|
||||
return original;
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
fence_before(order);
|
||||
uint32_t tmp;
|
||||
storage_type original, result;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
|
||||
"1:\n"
|
||||
"ldrex %[original], %[storage]\n" // original = *(&storage)
|
||||
"sub %[result], %[original], %[value]\n" // result = original - value
|
||||
"uxth %[result], %[result]\n" // zero extend result from 16 to 32 bits
|
||||
"strex %[tmp], %[result], %[storage]\n" // *(&storage) = result, tmp = store failed
|
||||
"teq %[tmp], #0\n" // flags = tmp==0
|
||||
"bne 1b\n" // if (!flags.equal) goto retry
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
|
||||
: [original] "=&r" (original), // %0
|
||||
[result] "=&r" (result), // %1
|
||||
[tmp] "=&l" (tmp), // %2
|
||||
[storage] "+Q" (storage) // %3
|
||||
: [value] "r" (v) // %4
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
||||
);
|
||||
fence_after(order);
|
||||
return original;
|
||||
}
|
||||
};
|
||||
|
||||
template< >
|
||||
struct operations< 2u, true > :
|
||||
public operations< 4u, true >
|
||||
{
|
||||
typedef operations< 4u, true > base_type;
|
||||
typedef base_type::storage_type storage_type;
|
||||
|
||||
static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
fence_before(order);
|
||||
uint32_t tmp;
|
||||
storage_type original, result;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
|
||||
"1:\n"
|
||||
"ldrex %[original], %[storage]\n" // original = *(&storage)
|
||||
"add %[result], %[original], %[value]\n" // result = original + value
|
||||
"sxth %[result], %[result]\n" // sign extend result from 16 to 32 bits
|
||||
"strex %[tmp], %[result], %[storage]\n" // *(&storage) = result, tmp = store failed
|
||||
"teq %[tmp], #0\n" // flags = tmp==0
|
||||
"bne 1b\n" // if (!flags.equal) goto retry
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
|
||||
: [original] "=&r" (original), // %0
|
||||
[result] "=&r" (result), // %1
|
||||
[tmp] "=&l" (tmp), // %2
|
||||
[storage] "+Q" (storage) // %3
|
||||
: [value] "r" (v) // %4
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
||||
);
|
||||
fence_after(order);
|
||||
return original;
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
fence_before(order);
|
||||
uint32_t tmp;
|
||||
storage_type original, result;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_START(%[tmp])
|
||||
"1:\n"
|
||||
"ldrex %[original], %[storage]\n" // original = *(&storage)
|
||||
"sub %[result], %[original], %[value]\n" // result = original - value
|
||||
"sxth %[result], %[result]\n" // sign extend result from 16 to 32 bits
|
||||
"strex %[tmp], %[result], %[storage]\n" // *(&storage) = result, tmp = store failed
|
||||
"teq %[tmp], #0\n" // flags = tmp==0
|
||||
"bne 1b\n" // if (!flags.equal) goto retry
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%[tmp])
|
||||
: [original] "=&r" (original), // %0
|
||||
[result] "=&r" (result), // %1
|
||||
[tmp] "=&l" (tmp), // %2
|
||||
[storage] "+Q" (storage) // %3
|
||||
: [value] "r" (v) // %4
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
||||
);
|
||||
fence_after(order);
|
||||
return original;
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
#if defined(BOOST_ATOMIC_DETAIL_ARM_HAS_LDREXD_STREXD)
|
||||
|
||||
// Unlike 32-bit operations, for 64-bit loads and stores we must use ldrexd/strexd.
|
||||
// Any other instructions result in a non-atomic sequence of 32-bit accesses.
|
||||
// See "ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition",
|
||||
// Section A3.5.3 "Atomicity in the ARM architecture".
|
||||
|
||||
// In the asm blocks below we have to use 32-bit register pairs to compose 64-bit values.
|
||||
// In order to pass the 64-bit operands to/from asm blocks, we use undocumented gcc feature:
|
||||
// the lower half (Rt) of the operand is accessible normally, via the numbered placeholder (e.g. %0),
|
||||
// and the upper half (Rt2) - via the same placeholder with an 'H' after the '%' sign (e.g. %H0).
|
||||
// See: http://hardwarebug.org/2010/07/06/arm-inline-asm-secrets/
|
||||
|
||||
template< bool Signed >
|
||||
struct operations< 8u, Signed > :
|
||||
public gcc_arm_operations_base
|
||||
{
|
||||
typedef typename make_storage_type< 8u, Signed >::type storage_type;
|
||||
typedef typename make_storage_type< 8u, Signed >::aligned aligned_storage_type;
|
||||
|
||||
static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
exchange(storage, v, order);
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
storage_type original;
|
||||
uint32_t tmp;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_START(%0)
|
||||
"ldrexd %1, %H1, [%2]\n"
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%0)
|
||||
: BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(tmp), // %0
|
||||
"=&r" (original) // %1
|
||||
: "r" (&storage) // %2
|
||||
);
|
||||
fence_after(order);
|
||||
return original;
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
storage_type original;
|
||||
fence_before(order);
|
||||
uint32_t tmp;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_START(%0)
|
||||
"1:\n"
|
||||
"ldrexd %1, %H1, [%3]\n" // load the original value
|
||||
"strexd %0, %2, %H2, [%3]\n" // store the replacement, tmp = store failed
|
||||
"teq %0, #0\n" // check if store succeeded
|
||||
"bne 1b\n"
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%0)
|
||||
: BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(tmp), // %0
|
||||
"=&r" (original) // %1
|
||||
: "r" (v), // %2
|
||||
"r" (&storage) // %3
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
|
||||
);
|
||||
fence_after(order);
|
||||
return original;
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE bool compare_exchange_weak(
|
||||
storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
|
||||
{
|
||||
fence_before(success_order);
|
||||
uint32_t tmp;
|
||||
storage_type original, old_val = expected;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_START(%0)
|
||||
"ldrexd %1, %H1, [%3]\n" // original = *(&storage)
|
||||
"cmp %1, %2\n" // flags = original.lo==old_val.lo
|
||||
"ittt eq\n" // [hint that the following 3 instructions are conditional on flags.equal]
|
||||
"cmpeq %H1, %H2\n" // if (flags.equal) flags = original.hi==old_val.hi
|
||||
"strexdeq %0, %4, %H4, [%3]\n" // if (flags.equal) *(&storage) = desired, tmp = store failed
|
||||
"teqeq %0, #0\n" // if (flags.equal) flags = tmp==0
|
||||
"ite eq\n" // [hint that the following 2 instructions are conditional on flags.equal]
|
||||
"moveq %2, #1\n" // if (flags.equal) old_val.lo = 1
|
||||
"movne %2, #0\n" // if (!flags.equal) old_val.lo = 0
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%0)
|
||||
: BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(tmp), // %0
|
||||
"=&r" (original), // %1
|
||||
"+r" (old_val) // %2
|
||||
: "r" (&storage), // %3
|
||||
"r" (desired) // %4
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
|
||||
);
|
||||
const uint32_t success = (uint32_t)old_val;
|
||||
if (success)
|
||||
fence_after(success_order);
|
||||
else
|
||||
fence_after(failure_order);
|
||||
expected = original;
|
||||
return !!success;
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE bool compare_exchange_strong(
|
||||
storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
|
||||
{
|
||||
fence_before(success_order);
|
||||
uint32_t tmp;
|
||||
storage_type original, old_val = expected;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_START(%0)
|
||||
"1:\n"
|
||||
"ldrexd %1, %H1, [%3]\n" // original = *(&storage)
|
||||
"cmp %1, %2\n" // flags = original.lo==old_val.lo
|
||||
"it eq\n" // [hint that the following instruction is conditional on flags.equal]
|
||||
"cmpeq %H1, %H2\n" // if (flags.equal) flags = original.hi==old_val.hi
|
||||
"bne 2f\n" // if (!flags.equal) goto end
|
||||
"strexd %0, %4, %H4, [%3]\n" // *(&storage) = desired, tmp = store failed
|
||||
"teq %0, #0\n" // flags.equal = tmp == 0
|
||||
"bne 1b\n" // if (flags.equal) goto retry
|
||||
"2:\n"
|
||||
"ite eq\n" // [hint that the following 2 instructions are conditional on flags.equal]
|
||||
"moveq %2, #1\n" // if (flags.equal) old_val.lo = 1
|
||||
"movne %2, #0\n" // if (!flags.equal) old_val.lo = 0
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%0)
|
||||
: BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(tmp), // %0
|
||||
"=&r" (original), // %1
|
||||
"+r" (old_val) // %2
|
||||
: "r" (&storage), // %3
|
||||
"r" (desired) // %4
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
|
||||
);
|
||||
const uint32_t success = (uint32_t)old_val;
|
||||
if (success)
|
||||
fence_after(success_order);
|
||||
else
|
||||
fence_after(failure_order);
|
||||
expected = original;
|
||||
return !!success;
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
fence_before(order);
|
||||
storage_type original, result;
|
||||
uint32_t tmp;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_START(%0)
|
||||
"1:\n"
|
||||
"ldrexd %1, %H1, [%3]\n" // original = *(&storage)
|
||||
"adds %2, %1, %4\n" // result = original + value
|
||||
"adc %H2, %H1, %H4\n"
|
||||
"strexd %0, %2, %H2, [%3]\n" // *(&storage) = result, tmp = store failed
|
||||
"teq %0, #0\n" // flags = tmp==0
|
||||
"bne 1b\n" // if (!flags.equal) goto retry
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%0)
|
||||
: BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(tmp), // %0
|
||||
"=&r" (original), // %1
|
||||
"=&r" (result) // %2
|
||||
: "r" (&storage), // %3
|
||||
"r" (v) // %4
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
|
||||
);
|
||||
fence_after(order);
|
||||
return original;
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
fence_before(order);
|
||||
storage_type original, result;
|
||||
uint32_t tmp;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_START(%0)
|
||||
"1:\n"
|
||||
"ldrexd %1, %H1, [%3]\n" // original = *(&storage)
|
||||
"subs %2, %1, %4\n" // result = original - value
|
||||
"sbc %H2, %H1, %H4\n"
|
||||
"strexd %0, %2, %H2, [%3]\n" // *(&storage) = result, tmp = store failed
|
||||
"teq %0, #0\n" // flags = tmp==0
|
||||
"bne 1b\n" // if (!flags.equal) goto retry
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%0)
|
||||
: BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(tmp), // %0
|
||||
"=&r" (original), // %1
|
||||
"=&r" (result) // %2
|
||||
: "r" (&storage), // %3
|
||||
"r" (v) // %4
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
|
||||
);
|
||||
fence_after(order);
|
||||
return original;
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
fence_before(order);
|
||||
storage_type original, result;
|
||||
uint32_t tmp;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_START(%0)
|
||||
"1:\n"
|
||||
"ldrexd %1, %H1, [%3]\n" // original = *(&storage)
|
||||
"and %2, %1, %4\n" // result = original & value
|
||||
"and %H2, %H1, %H4\n"
|
||||
"strexd %0, %2, %H2, [%3]\n" // *(&storage) = result, tmp = store failed
|
||||
"teq %0, #0\n" // flags = tmp==0
|
||||
"bne 1b\n" // if (!flags.equal) goto retry
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%0)
|
||||
: BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(tmp), // %0
|
||||
"=&r" (original), // %1
|
||||
"=&r" (result) // %2
|
||||
: "r" (&storage), // %3
|
||||
"r" (v) // %4
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
|
||||
);
|
||||
fence_after(order);
|
||||
return original;
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
fence_before(order);
|
||||
storage_type original, result;
|
||||
uint32_t tmp;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_START(%0)
|
||||
"1:\n"
|
||||
"ldrexd %1, %H1, [%3]\n" // original = *(&storage)
|
||||
"orr %2, %1, %4\n" // result = original | value
|
||||
"orr %H2, %H1, %H4\n"
|
||||
"strexd %0, %2, %H2, [%3]\n" // *(&storage) = result, tmp = store failed
|
||||
"teq %0, #0\n" // flags = tmp==0
|
||||
"bne 1b\n" // if (!flags.equal) goto retry
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%0)
|
||||
: BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(tmp), // %0
|
||||
"=&r" (original), // %1
|
||||
"=&r" (result) // %2
|
||||
: "r" (&storage), // %3
|
||||
"r" (v) // %4
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
|
||||
);
|
||||
fence_after(order);
|
||||
return original;
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
fence_before(order);
|
||||
storage_type original, result;
|
||||
uint32_t tmp;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_START(%0)
|
||||
"1:\n"
|
||||
"ldrexd %1, %H1, [%3]\n" // original = *(&storage)
|
||||
"eor %2, %1, %4\n" // result = original ^ value
|
||||
"eor %H2, %H1, %H4\n"
|
||||
"strexd %0, %2, %H2, [%3]\n" // *(&storage) = result, tmp = store failed
|
||||
"teq %0, #0\n" // flags = tmp==0
|
||||
"bne 1b\n" // if (!flags.equal) goto retry
|
||||
BOOST_ATOMIC_DETAIL_ARM_ASM_END(%0)
|
||||
: BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(tmp), // %0
|
||||
"=&r" (original), // %1
|
||||
"=&r" (result) // %2
|
||||
: "r" (&storage), // %3
|
||||
"r" (v) // %4
|
||||
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
|
||||
);
|
||||
fence_after(order);
|
||||
return original;
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
return !!exchange(storage, (storage_type)1, order);
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
store(storage, 0, order);
|
||||
}
|
||||
|
||||
static BOOST_FORCEINLINE bool is_lock_free(storage_type const volatile&) BOOST_NOEXCEPT
|
||||
{
|
||||
return true;
|
||||
}
|
||||
};
|
||||
|
||||
#endif // defined(BOOST_ATOMIC_DETAIL_ARM_HAS_LDREXD_STREXD)
|
||||
|
||||
|
||||
BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
if (order != memory_order_relaxed)
|
||||
gcc_arm_operations_base::hardware_full_fence();
|
||||
}
|
||||
|
||||
BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
|
||||
{
|
||||
if (order != memory_order_relaxed)
|
||||
__asm__ __volatile__ ("" ::: "memory");
|
||||
}
|
||||
|
||||
} // namespace detail
|
||||
} // namespace atomics
|
||||
} // namespace boost
|
||||
|
||||
#endif // BOOST_ATOMIC_DETAIL_OPS_GCC_ARM_HPP_INCLUDED_
|
||||
Reference in New Issue
Block a user